The present invention relates to semiconductor integrated circuits and a method for controlling semiconductor integrated circuits.
The frequency of a controller (CPU) that controls a dynamic random access memory (DRAM) is high and has been increasing. Thus, external commands are generated at high speed cycles by the controller and the DRAM is required to process such high speed external commands.
A synchronous DRAM has thus been proposed to receive the high speed external command synchronously with either a first internal clock signal or a second internal clock signal. More specifically, the DRAM divides the high frequency external clock signal from the controller in half. The phases of the divided signal are offset from each other by 180xc2x0. As a result, a first internal clock signal and a second internal clock signal having phases offset from each other by 180xc2x0 are generated. The DRAM receives the external command in synchronism with an external clock signal when either the first internal clock signal or the second internal clock signal rises.
The DRAM includes a first signal processing circuit for processing an external command received synchronously with the first internal clock signal and a second signal processing circuit for processing an external command received synchronously with the second internal clock signal. The first and second signal processing circuits process external commands separately so that the high speed external commands can be followed.
However, such processing of the external commands has the shortcomings described below.
(1) Invalidation of the external commands from the DRAM controller may be delayed in accordance with the wire length and wire capacitance. In such case, the first and second signal processing circuits must receive an external command that is the same as the previous command and process the command once more. This hinders accurate decoding of the external command.
(2) When the input cycle of the external command is altered, the frequency of the first and second internal clock signal is varied. The varied first and second internal clock signals may result in the first and second signal processing circuits receiving an external command that is the same as the previous external command.
(3) Fluctuations in the temperature or power supply voltage may vary the frequency of the first and second internal clock signals. In such case, the first and second signal processing circuits may receive an external command that is the same as the previous external command.
Accordingly, it is an objective of the present invention to provide a semiconductor memory device that processes external commands accurately.
To achieve the above objective, the present invention provides a method for controlling a semiconductor integrated circuit device having a plurality of signal processing circuits, which process an input signal. The method includes the steps of receiving the input signal in one of the plurality of signal processing circuits and outputting an internal signal in response to a clock signal, and prohibiting another of the signal processing circuits from processing the input signal for a predetermined time in response to the internal signal.
In a further aspect of the present invention, a semiconductor integrated circuit device is provided. The device includes a plurality of signal processing circuits for processing an input signal. A prohibiting circuit is connected to the plurality of signal processing circuits. The prohibiting circuit prohibits another of the signal processing circuits from processing the input signals for a predetermined time in response to an internal signal which is output from one of the signal processing circuit based on the input signal.
In another aspect of the present invention, a semiconductor memory device is provided. The device includes a plurality of input buffers for receiving an external command in synchronism with a plurality of internal clock signals. A command decoder is connected to the plurality of input buffers to receive the external commands from the input buffers, decoding the external command, and generating internal commands. The command decoder has a plurality of decoding circuits. Each of the decoding circuits decodes the external commands in accordance with an associated one of the plurality of internal clock signals. A mask circuit is connected to the plurality of decoding circuits. The mask circuit prevents another of the decoding circuits from decoding the external command for a predetermined time when one of the decoding circuits decodes the external command.